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[VHDL-FPGA-Verilog] UART

Description: the uart transmitter and receiver are used to design the data transmission for 8bit sipo and piso in verilog
Platform: | Size: 1024 | Author: prabakaran | Hits:

[Other] uart_rx

Description: Tcode is in VERILOG HDL (Hardware description language) code is of UART (universal asynchronous receiver&transmitter) receiver . its objective is to accept serial data from port of computer and allow it to come in a FPGA-Tcode is in VERILOG HDL (Hardware description language) code is of UART (universal asynchronous receiver&transmitter) receiver . its objective is to accept serial data from port of computer and allow it to come in a FPGA
Platform: | Size: 1024 | Author: hassan | Hits:

[VHDL-FPGA-Verilog] verilog_rs232

Description: 用verilog实现串行口UART控制器，适用于XILINX器件-verilog UART controller
Platform: | Size: 343040 | Author: bigchop ma | Hits:

[VHDL-FPGA-Verilog] uart

Description: RS232控制分频,实现占空比和频率可以控制的分频器-verilog RS232
Platform: | Size: 79872 | Author: cuiqiang | Hits:

[VHDL-FPGA-Verilog] uart

Description: 自己写的Verilog写的串口程序，实现收发功能。方法不错，可以参考下。-verilog...uart...
Platform: | Size: 538624 | Author: 地主 | Hits:

[VHDL-FPGA-Verilog] uart1

Description: RS232(UART)串口传输，通过了FPGA验证功能正确-UART RS232 verilog HDL FPGA xilinx
Platform: | Size: 237568 | Author: 徐 | Hits:

[VHDL-FPGA-Verilog] uart_verilog

Description: UART Verilog，书中里的例子，绝对正确，用Verilog语言编写的串口通信例子-UART VerilogCommand Parsing NiosII serial serial parts, including the interruption, send the command prompt, receiving treatment and other characters. Spent a lot of hard work! Definitely useful for beginners
Platform: | Size: 4096 | Author: 李燕乐 | Hits:

[Program doc] UART_spec

Description: a UART model with FIFO buffer, design with verilog
Platform: | Size: 145408 | Author: quang | Hits:

[VHDL-FPGA-Verilog] uart16550

Description: Implementation of the UART 16550 model with verilog langugue
Platform: | Size: 40960 | Author: quang | Hits:

[Program doc] SPI-in-Verilog-implementation

Description: SPI的Verilog实现(非常的全面和详细，还带有SPI算法的注解).-SPI in Verilog implementation (a very full and detailed, but also with the SPI algorithm annotation).
Platform: | Size: 8192 | Author: 尚林 | Hits:

[VHDL-FPGA-Verilog] sim_uart

Description: uart 收发器 verilog 代码，实现自收发功能 sys clk = 25m, baud 9600 停止位1， 无校验位； 代码实现了串口自收发功能，及把从 PC 收到的内容都发送会 PC, 其他波特率，自行修改代码即可，在 alter 的FPGA 上调试通过； -verilog code uart transceiver to achieve self-transceiver function sys clk = 25m, baud 9600 1 stop bit, no parity code from the transceiver features a serial port, and the contents received from the PC will send the PC, another Potter rate, self-modifying code can, in the alter of the FPGA, debugging through
Platform: | Size: 2048 | Author: 周西东 | Hits:

[VHDL-FPGA-Verilog] RS232

Description: It s combination logic for UART. Edited in verilog-HDL.
Platform: | Size: 5120 | Author: kim | Hits:

[VHDL-FPGA-Verilog] uart

Description: uart IP CORE Verilog quartus-uart IP CORE Verilog quartusii
Platform: | Size: 36864 | Author: thegreeneyes | Hits:

[VHDL-FPGA-Verilog] Verilog-UART

Description: UART With Verilog Unit for Transmission Unit for Reception
Platform: | Size: 93184 | Author: Rami | Hits:

[VHDL-FPGA-Verilog] UART

Description: FPGA的UART程序，非常好的，讲解详细，我当初看了好多都看不懂，看了这个以后终于明白-FPGA' s UART program, very good, detailed explanation, I had read a lot have not read, finally realized after reading this
Platform: | Size: 276480 | Author: xuxing | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 这是一个uart串口实现16550的实现，代码已测试过了。-This is a 16550 uart serial port, the code has been tested before.
Platform: | Size: 35840 | Author: wangli | Hits:

[VHDL-FPGA-Verilog] uartverilog

Description: 用verilog语言编写uart程序。模拟串口时序进行收发数据操作。-verilog uart
Platform: | Size: 313344 | Author: 一贯故 | Hits:

[VHDL-FPGA-Verilog] uart-

Description: 通用异步通讯UART的工程文档，ISE打开工程，里面有VERILOG的源代码，可以编译通过-UART Universal Asynchronous communication engineering documents, ISE open the project, which has VERILOG source code can be compiled
Platform: | Size: 30720 | Author: mike | Hits:

[VHDL-FPGA-Verilog] UART

Description: verilog 串口模块，高度集成，下载下就能用-verilog uart communication,easy use
Platform: | Size: 31744 | Author: zyy | Hits:

[VHDL-FPGA-Verilog] UART

Description: xilinx官网提供的VHDL,UART串行通信模块，肯定好用，官方提供-xilinx official website provides VHDL, UART, FPGA communication module is certainly easy to use, official
Platform: | Size: 10240 | Author: 雪尘 | Hits:
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